The use of a voltage-controlled oscillator (VCO) in phase-locked loop (PLL) designs is well known in the art and such designs are widely employed in radio, telecommunication, computer, and other electronic applications. In electronic systems that use PLLs, the time required for a PLL to tune, that is to achieve lock, is usually important to its operation.
The time for a PLL to tune is dependent upon a number of factors, such as the loop's bandwidth, voltage slew, damping factor, frequency step size, etc. In particular, voltage slew time on the PLL can impose a hard limit on how fast tuning can take place, which is especially troublesome with VCOs that have a large voltage range on the tune line. In addition, fast tuning capabilities may introduce multiple types of noise on the VCO tune line, including filtering noise, VCO interferences, phase noise, and spurs. In general, as tuning time decreases, the sensitivity of the PLL increases, and thus, becomes more susceptible to low noise levels and spurs.
Attempts have been made to improve PLL tuning time without introducing excess noise in the output signal. For example, several existing PLL designs use a coarse tuning technique in which a coarse tuning circuit provides the majority of voltage slew and a fine tuning circuit provides the remaining voltage slew. However, many existing coarse tune circuits require a VCO having two tune lines (a coarse tune line and a fine tune line) and/or other additional circuitry, which may be expensive. In addition, existing coarse tune circuits are vulnerable to imposing excess phase noise on the VCO tune line.